Double intracavity contacted long-wavelength VCSELs and method of fabricating same

ABSTRACT

A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.

[0001] The contents of this application are related to those provisional applications having serial Nos. 60/227,165, 60/227,161, and 60/226,866, filed Aug. 22, 2000, and a provisional application having serial No. 60/262,541, filed Jan. 16, 2001. The present application claims priority to these related provisional patent applications and their contents are hereby incorporated by reference in their entirety into the present disclosure. The contents of this application are also related to several nonprovisional patent applications being filed concurrently herewith. These nonprovisional patent applications are hereby incorporated by reference in their entirety and have the following attorney docket reference numerals: 510015-263, 510015-264, 510015-265, 510015-266, 510015-268, 510015-269, 510015-270, 510015-271, and 510015-272.

[0002] This invention was made with the support of the United States Government under Grant No. MDA972-98-1-0001, awarded by the Department of Defense (DARPA). The Government has certain rights in this invention under 35 U.S.C. §202.

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The invention relates in general to a vertical cavity surface emitting laser (VCSEL). More particularly, the invention relates to double-intracavity contacted long-wavelength vertical cavity lasers.

[0005] 2. General Background and State of the Art

[0006] Semiconductor lasers are widely used in optical applications, in part because semiconductor fabrication techniques are relatively inexpensive and yield reliable, consistent results. Also, they are easily packaged into current microelectronics. A relatively new class of semiconductor lasers, vertical cavity surface emitting lasers (VCSELs), has been developed through the evolution of this technology. Unlike conventional edge emitting lasers that emit light in a direction parallel to the semiconductor substrates where the lasers are formed, VCSELs have optical cavities perpendicular to the substrate, and thus emit optical radiation in a direction perpendicular to the substrate and perpendicular to a p-n junction formed between layers grown on the substrate. In addition to various performance and application-adaptable improvements created thereby, VCSELs simply require reduced complexity in their fabrication and testing, as compared to conventional edge emitting semiconductor lasers.

[0007] Vertical cavity surface emitting lasers (VCSELs) have been proven to be solutions for low-cost transmitters for high-speed data communications at 980 nm and 850 nm and have shown great potential for cost-effective telecommunication systems at longer wavelengths as well, such as 1.55 μm and 1.3 μm. These long wavelength VCSELs will satisfy increasing demand for high speed data transmission over tens of kilometers. 10-Gigabit Ethernet is one example, which requires inexpensive transmitters with a data rate of 10 G bit per second (Gbps) and up to 40 km reach over single-mode fiber.

[0008] VCSELs are semiconductor lasers having a semiconductor layer of optically active material, such as gallium arsenide or indium gallium arsenide or the like, sandwiched between highly-reflective layers of metallic material, dielectric material, epitaxially-grown semiconductor dielectric material or combinations thereof, most frequently in stacks. As is conventional, one of the mirror stacks is partially reflective so as to pass a portion of the coherent light built up in the resonating cavity formed by the mirror stack/active layer sandwich. Laser structures require optical confinement and carrier confinement to achieve efficient conversion of pumping electrons to stimulated photons (a semiconductor may lase if it achieves population inversion in the energy bands of the active material.)

[0009] While both short wavelength and long wavelength VCSELs have proven to offer excellent solutions for many applications in the evolving optical applications marketplace, they also have certain limitations and drawbacks that are well known in the art. Some of the drawbacks are associated with the need to electrically pump as well as conduct heat through the multi-layer mirror stacks, which exhibit poor electrical and thermal conductivities. Other drawbacks to VCSEL performance include high threshold current and high operating voltage. Mirror stacks lattice-matched to InP, as desired for high-reliability long wavelength operation, have limited thermal conductivity, and if doped sufficiently to provide useful electrical conductivity, also create excessive optical loss.

INVENTION SUMMARY

[0010] The present invention provides a novel approach to overcoming the drawbacks of existing VCSELs by presenting a double intracavity contacted VCSEL having a selectively apertured active region. The present invention provides a new design and method of manufacture allowing for room temperature, continuous-wave (CW) operation of AsSb-based VCSELs by providing thick indium phosphide (InP) cladding layers having very thin heavily-doped contact layers in a double-intracavity structure.

[0011] The present invention has several features combined together resulting in improved thermal characteristics as well as reduced current and optical losses. These combined features include:

[0012] 1. thick n-type cladding layers;

[0013] 2. very thin, heavily-doped, n-typed contact layers and a very thin, heavily-doped, tunnel junction; and

[0014] 4. an aperture formed from the active region.

[0015] The thick, n-type cladding layers provide low-impedance current and heat paths avoiding conduction through poor optically and electrically conducting distributed Bragg reflectors, also known as DBRs or Bragg mirrors. The low-impedance heat path reduces the device temperature. The low-impedance current path results in a lower device operating voltage which also reduces the device temperature. Because the current path is through the cladding layers, there is no need to dope the DBRs and substrate, resulting in reduced free carrier absorption and reduced optical loss. Optical loss is also decreased because the cladding layers are n-type rather than p-type.

[0016] The very thin, heavily-doped n-type contact layers lower the impedance of the current path by providing better electrical contact with attached contacts. The heavily-doped tunnel junction provides a hole source allowing both cladding layers to be substantially n-type, reducing optical loss and decreasing impedance. The heavily-doped contact layers are thin, reducing optical loss since the majority of the contact layer volume can be doped at a lower level. Additionally, the heavily-doped contact layers are located at standing-wave nulls in the laser cavity, reducing free carrier absorption. Selective etchings enable the exposure of such thin, heavily doped, contact and tunnel junction layers.

[0017] The aperture formed in the active region confines the current to the desired area of the active region, reducing the device voltage. The optical mode is also confined, reducing optical loss and lowering the threshold current. The optical mode is confined by the aperture, resulting in reduced optical loss at the sidewall of the etched-pillar DBR, lower threshold current, lower threshold current density, larger differential quantum efficiency and higher output power.

[0018] The method of increasing the processing efficiency of a VCSEL also includes removing a first, or top, DBR by applying a first selective etch, removing a first, or top, cladding layer by applying a second selective etch, and removing the active region by applying a third selective etch to form an undercut aperture in the active region into which electric current can be confined. Additionally, the present invention further provides the first room temperature, continuous-wave (CW) operation of a 1.55-μm vertical-cavity surface-emitting laser (VCSEL) that is completely lattice-matched to InP and produced in one epitaxial growth.

[0019] Accordingly, it is one object of the present invention to provide for room temperature, continuous-wave (CW) operation of AsSb-based VCSELs by including indium phosphide (InP) cladding layers having very thin heavily-doped contact layers in a double-intracavity structure. It is another object of the invention to provide a method of increasing the processing efficiency of a VCSEL by selectively etching an undercut aperture into the active region and injecting current into the active region.

[0020] Another object of the present invention is to provide a room temperature, continuous-wave (CW) operation of a 1.55-μm vertical-cavity surface-emitting laser (VCSEL) that is completely lattice-matched to InP and produced in one epitaxial growth.

[0021] Other objects of the present invention are to reduce elevated temperatures in the VCSEL, minimize optical loss associated with heavily-doped contact layers, reduce threshold current and operating voltage, and improve thermal conductivity and electrical resistivity in the VCSEL.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is schematic representation of double intracavity contacted, long wavelength VCSEL;

[0023]FIG. 2 is a table showing thermal conductivity and electron and hole mobility of various materials used in VCSEL design;

[0024]FIG. 3 is a plot of standing wave distribution in a 3.5λ cavity of a double intracavity contacted VCSEL;

[0025]FIG. 4 is a schematic representation of a selective etch process of producing the VCSEL of the present invention;

[0026]FIG. 5 is a close-up schematic representation of a VCSEL having contacts placed at positions where selective etches have removed portions of the VCSEL structure;

[0027]FIG. 6 is a schematic representation of a VCSEL showing the flow of current and heat through contacts and cladding layers;

[0028]FIG. 7 is a picture of a VCSEL having an undercut aperture formed by selectively etching the active region;

[0029]FIG. 8 is a plot of continuous wave light characteristics of a double intracavity contacted VCSEL with 16 μm pillar and 8 μm aperture;

[0030]FIG. 9 is a plot threshold current density vs. temperature of a double intracavity contacted VCSEL for pulsed operation;

[0031]FIG. 10 is a plot of lasing spectrum at 7.5 times threshold for a double intracavity contacted VCSEL;

[0032]FIG. 11(a) is a plot of operating voltage for a double intracavity contacted VCSEL with 8 μm or 12 μm aperture;

[0033]FIG. 11(b) is a plot of thermal impedance vs. aperture diameter for a double intracavity contacted VCSEL with 16 μm pillar;

[0034]FIG. 12 is a plot of temperature rise in a double intracavity contacted VCSEL with 16 μm pillar and 8 μm aperture and a plot of temperature rise in air-post VCSELs (where current is injected through DBRs);

[0035]FIG. 13(a) is a plot of light output characteristics of a double intracavity contacted VCSEL with 16 μm pillar and 8 μm or 12 μm aperture;

[0036]FIG. 13(b) is a plot of light output characteristics of a double intracavity contacted VCSEL with a 10 μm aperture and 16 μm (solid) pillar or 12 μm (dashed) pillar;

[0037]FIG. 14 is graphical representation showing the reduction in thermal impedance in a VCSEL with flip-chip bonding;

[0038]FIG. 15 is a schematic representation of the application of a 5 V DC power supply to a VCSEL in a solution of citric peroxide;

[0039]FIG. 16 is a diagrammatic view of a portion of a VCSEL illustrating a tunnel junction and contact layers;

[0040]FIG. 17 graphically illustrates optical output power and voltage as a function of current through the VCSEL;

[0041]FIG. 18 graphically illustrates resistivity and optical loss as a function of doping level for the Silicon doped InP;

[0042]FIG. 19 illustrates I-V plots for three different types of tunnel junctions;

[0043]FIG. 20 provides an estimate of the current density versus distance dependence which is derived for an InP current spreading layer with an InP/InAlAs tunnel junction; and

[0044]FIG. 21 illustrates the injected current path crowded at the edges of the aperture.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045]FIG. 1 is a schematic representation of a long wavelength VCSEL 10 having two InP layers 12 a, 12 b cladding an InAlGaAs-based active region 14, such that the active region 14 is disposed between the two InP layers 12 a, 12 b to form a double intracavity contacted structure. A tunnel junction 16 located between one of the InP layers 12 a and the active region 14 generates holes for quantum wells in the active region 14 and allows both of the InP cladding layers 12 a, 12 b to be n-type. Only the InP cladding layers 12 a, 12 b, the tunnel junction 16 and part of the active region 14 are doped. Holes are created by the extraction of electrons from the valence band of a p-type layer in the tunnel junction 16. This design allows for the two n-type cladding layers 14 which have both higher electrical conductivity and lower optical loss than similarly-doped p-type layers. The tunnel junction 16 itself is at a standing-wave null of the cavity mode to minimize the absorption associated with the higher doping at this interface. The VCSEL 10 also includes first and second Sb-based mirror portions 18, 20 (also called a distributed Bragg reflector, or DBR). The contact scheme enables current to be injected through the InP cladding layers 12 a, 12 b and bypass the first and second mirror portions 18, 20, and it eventually reduces series resistance of the VCSEL. The DBRs 18 and 20 are undoped, Sb-based multi-layered structures and may include alternating layers of aluminum arsenic antimonide (AlAsSb) and aluminum gallium arsenic antimonide (AlGaAsSb).

[0046] The double intracavity contacted structure also allows heat generated inside the VCSEL 10 to bypass the first and second mirror portions 18 and 20 in the same manner with the injected current, such that most of the heat comes out of the VCSEL 10 through the two InP cladding layers 12 a, 12 b and contacts 22. This provides the VCSEL 10 with low thermal impedance in spite of the fairly low thermal conductivity of the Sb-based DBRs. The high electron mobility and the high thermal conductivity of InP provides low electrical and thermal impedance for the VCSEL 10 and prevents the VCSEL 10 from over-heating. Low electrical and thermal impedance is very useful for VCSELs operating at long wavelengths where a dominant non-radiative recombination process is an Auger recombination, which reduces injection efficiency and increases exponentially with temperature. FIG. 2 is a table detailing the thermal conductivities and electron and hole mobilities of materials in the design of the double intracavity contacted VCSEL 10.

[0047] The intracavity contacts allow the VCSEL 10 to utilize undoped DBRs 18 and 20 and an undoped substrate 32, reducing free-carrier absorption in the VCSEL 10. The free-carrier absorption is further reduced by the decreasing doping level of the n-type InP cladding layers 12 a, 12 b without significant increase of the series resistance due to the high electron mobility of InP. In the double intracavity contacted design, scattering loss at the sidewall of the DBRs must also be minimized. The scattering loss is reduced by employing an undercut etched aperture smaller than the etched pillar formed by the first and second mirror portions 18, 20. An oxide aperture may also be used to provide current as well as optical confinement for shorter-wavelength Ga-based VCSELs. In the double intracavity design, however, an undercut etched aperture is employed instead of an oxide aperture and is formed by selectively etching an InAlGaAs-based active region with a mixture of citric acid and hydrogen peroxide as discussed herein. An advantage of an undercut aperture is that this constrains current exactly into the desired area of the active region, and there is no current spreading between the current aperture and the active region as is seen in oxide apertures. Surface-recombination appears to be low in the 1.55 μm active regions.

[0048] The double intracavity contacted long wavelength VCSEL 10 may be grown in a single step using molecular beam epitaxy in which the whole structure is completely lattice-matched to InP. In one embodiment, the first and second DBRs 18 and 20 use 30.5 periods and 21.5 periods of Al_(0.15)Ga_(0.85)As_(0.58)Sb_(0.42)/As_(0.56)Sb_(0.44), respectively. This material combination has an index contrast of 0.47, which brings a calculated reflectivity of >99.9% for the first DBR 18. The measured transmission of the second DBR 20 is 1.2%. The 1.5 λ-thick InP cladding layers 12 a, 12 b located on the top and bottom of the active region 14 are both n-type doped 5×10¹⁷ cm⁻³with silicon (Si), with top surface contact layers 10 nm thick doped 5×10¹⁸ cm⁻³with Si. InP doped with Si to a level of 5×10¹⁷ cm⁻³ has an absorption coefficient of 2.5 cm⁻¹. An n-type layer of the tunnel junction 16 is 20 nm of InP doped 3×10¹⁹ cm⁻³ with Si, and a p-type layer is 20 nm of AlInAs doped 1×10²⁰ cm⁻³ with carbon (C).

[0049] The active region 14 is based on an AlGaInAs material system and includes five strain compensated InAlGaAs quantum wells. This active region 14 has large conduction band offsets and is promising for high temperature operation. With this active region 14, 10 Gbps operation at high temperatures (85° C.) has been demonstrated using an uncooled ridge waveguide laser. The whole cavity including the active region 14 and InP cladding layers 12 a, 12 b is 3.5 λ thick. The grown cavity has a resonance wavelength of 1550 nm, the active region 14 has a photo luminescence peak of 1510 nm, and this gain offset puts the threshold minimum around room temperature.

[0050]FIG. 3 is a plot of the standing wave distribution of a VCSEL 10, in which three arrows indicate the positions of heavily-doped layers. All heavily-doped layers, i.e. the InP cladding layers 12 a, 12 b and tunnel junction 16, are located at standing-wave nulls in the laser cavity, so that free-carrier absorption is reduced as much as possible.

[0051]FIG. 4 is schematic representation of the process of fabricating a double intracavity, long wavelength VCSEL 10. Exposing the InP contact layers 13, 21 of the cladding layers 12 a, 12 b (see FIG. 16) is one of the most critical steps in the fabrication process of the double intracavity contacted VCSEL. The contact layers 13, 21 must be exposed to allow for current to be injected through contacts 22. To expose the first contact layer, a portion of the top mirror is removed. To expose the second contact layer 21, portions of the cladding layer 12 a and active region 14 are then removed. The contacts 22 may be made of metals that include but are not limited to nickel, gold, germanium and/or other conducting materials.

[0052] Since the contact layer thickness should be minimized to reduce free carrier absorption in the cavity, the various selective etches are used to control etching depth precisely when the contact layers are exposed. To reach the first InP cladding layer 12 a at least a portion of the first mirror portion 18 is removed. For long wavelength VCSELs 10 grown epitaxially on InP, these DBRs 18 are typically AlGaAs, InAlGaP or AlGaAsSb-based. A first selective etch 24 is a low voltage reactive ion etch (RIE) using chlorine (Cl₂)gas that etches through either type of DBR 18 but does not etch the InP cladding layer 12 a, so that the etching stops at the very top of the cladding layer 12 a. This transition is caused by the formation of a non-volatile InCl₂ layer on the surface of the contact layer 13 and is easily identified during the RIE using an in-situ laser monitor. Although the selectivity of AlGaAsSb to InP is not so large (around 6:1), the RIE exposes the very thin (10 nm) top contact layer 13 by combining the selective RIE with the in-situ monitoring.

[0053] The first etch 24, therefore, stops exactly where the first contact 22 for the double intracavity VCSEL 10 is deposited. The first contact layer 13 is therefore very thin (<100 Å), minimizing the optical loss associated with this layer.

[0054] A second InP cladding layer 12 b lies below the first InP cladding layer 12 a and the active region 14. By choosing a AlInGaAs-based active region, common in long-wavelength lasers, two more selective etches can be employed to reach this second cladding layer 12 b without excessive processing difficulty.

[0055] A second selective etch 26, which is a RIE which includes methane and hydrogen (CH₄/H₂) gases and which is standard for InP etching, removes at least a portion of the first InP cladding layer 12 a but stops on the top InAlAs layer of the active region 14. Selectivity of this second selective etch is, in one embodiment, a 16:1 selectivity. In one embodiment, argon (Ar) gas may also be used in combination with methane and hydrogen in the second selective etch 26. In another embodiment, nitrogen (N₂) gas may also be used in combination with methane and hydrogen. A third selective etch 28, which includes a mixture of citric acid and hydrogen peroxide, then removes at least a portion of the InAlGaAs active region but does not etch the second contact layer 21 (see FIG. 16) with a selectivity of more than 100:1. In one embodiment, the selectivity of this third etch is 80:1. This InP contact layer of the cladding layer 12 b, therefore, can also be confined to the top 100 Å. The third selective etch 28 is also used to undercut the active region to aperture the VCSEL 10.

[0056]FIGS. 5 and 6 are schematic representations of VCSELs 10 having contacts 22 placed at positions where the above selective etches have removed portions of the VCSEL structure. FIG. 5 shows a diagrammatic representation of an circuit model in the VCSEL. FIG. 6 shows a diagrammatic representation of a VCSEL 10 having contacts 22. As voltage is applied across the contacts 22, a current path 29 flows through the contacts 22, the InP cladding layers 12 a, 12 b and the apertured active region 14 such that the current 29 is constrained in the middle of the active region 14 due to the etched away portion at the side of the active region. The heat flows through the heat path 31.

[0057] In an alternative embodiment, the cladding layer 12 b is not used as an intracavity contact. Rather, the current path extends from the contact 22 of the cladding layer 12 a and through the substrate 32. In this embodiment the substrate 32 and mirror 20 should be doped to provide a conductive path. This embodiment maintains some thermal benefits of the cladding layers 12 a, 12 b and undoped top mirror 18. Advantages of an undoped bottom mirror 20 and undoped substrate 32 along with the bipassing of the current flow away from the mirror 20 are compromised in favor of extra fabrication simplifications. The cladding layer 12 b can be kept in the structure to serve as a heat spreading layer even though not used as an intracavity contact. Alternatively, the cladding layer 12 b can be removed from the structure to provide further fabrication simplifications.

[0058]FIG. 7 is a close-up picture of a VCSEL 10 having an etched gap 30. The etched gap 30 creates the undercut aperture having a disk-like shape etched in the active region 14. An undercut aperture 14 is utilized in the VCSEL 10 to constrain injected current into the area underneath the etched-pillar DBR and minimize optical scattering loss at its sidewall. The citric acid-hydrogen peroxide mixture of the third etch 28 selectively etches InAlGaAs and not InP, forming the undercut aperture 30. The selectivity (>100:1) is large enough so that the undercut aperture deeper than 10 μm can be formed with little decrease of the InP cladding layers 12 a, 12 b. This third etch 28 also shows selectivity between InAlAs and InGaAs, and it produces a slight tapered aperture as seen in FIG. 7. The etching depth was monitored using circular InP bumps with different diameters which sit on the same wafer with the devices. These InP bumps have an InAlGaAs layer, the same layer as the active region, and this InAlGaAs layer is also etched when the undercut aperture 30 is formed. The undercut depth was determined by checking the diameter of the largest bump which was etched off.

[0059] The undercut aperture is formed by selectively etching the active region after the other layers have been etched by other selective etches. The undercut aperture is formed as the third selective etch is applied from the outside of the VCSEL 10 toward the inside of the active region from either side. Thus, an undercut aperture is formed by etching away portions of the active region from the outside and working inward toward the center of the VCSEL structure.

[0060] In another embodiment, the VCSEL 10 may be etched beginning with a substrate 32, followed by the bottom mirror portion 20 such that the VCSEL 10 is etched from the bottom up to the active region 14. After etching at least a portion of the substrate 32 and at least a portion of the bottom DBR 20, at least a portion of the bottom cladding layer 12 b is then etched to allow access to the active region 14. The active region 14 is then etched by applying the citric acid-hydrogen peroxide third selective etch 28 and aperturing a portion of the active region to allow current 29 to be constrained into the center of the active region 14.

[0061]FIG. 8 is a plot of the L-l characteristics of the VCSEL 10 with a 16 μm etched pillar and an 8 μm undercut aperture, measured at various temperatures under both continuous wave and pulsed operation. At 25° C., the threshold current and threshold density are 800 μA and 1.6 kA/cm², respectively, and the differential quantum efficiency is 23% at maximum. The maximum continuous wave output power is 1.05 mW at 20° C. and 110 μW at 88° C., and the VCSEL 10 operates up to 88° C. FIG. 9 is a plot of the threshold current density under pulsed operation as a function of temperature. The threshold current density is minimized at about 25° C., indicating that the gain peak wavelength matches the cavity mode at this temperature. Larger gain offset will increase the maximum operation temperature as well as the output power at high temperature. The lasing spectrum is also measured. FIG. 10 is a plot of lasing spectrum at 7.5 times threshold for a double intracavity contacted VCSEL 10. A VCSEL 10 with 14 μm etched pillar and an 8 μm aperture lases at 1.56 μm and shows a single-mode operation up to its maximum output, and the side-mode suppression ration is 39 dB. From FIG. 10, it is seen that the smaller pillar adds some level of mode selective loss.

[0062] These excellent results, such as high temperature operation and high output power, are attributed to three primary benefits resulting from the VCSEL structure of the present invention: low operating voltage, low thermal impedance, and low scattering loss.

[0063] Low values of operating voltage and thermal impedance result from the double intracavity-contacted structure with the thick, n-type InP layers. FIGS. 11(a) and 11(b) show graphical representations of additional benefits of using InP cladding layers in VCSEL design. FIG. 11(a) is a plot of operating voltage for a double intracavity contacted VCSEL showing injected current vs. voltage characteristics for different aperture diameters. FIG. 11(b) is a plot of the thermal impedance as a function of aperture diameter. Both figures also show the data for air-post VCSELs, in which current is injected through the Sb-based DBRs. The double intracavity contacted design provides much lower electrical and thermal impedance when compared with air-post VCSELs. FIG. 12 is a plot of temperature rise in a double intracavity contacted VCSEL with 16 μm pillar and 8 μm aperture and a plot of temperature rise in air-post VCSELs. The double intracavity-contacted VCSEL with a 16 μm pillar and an 8 μm aperture shows a threshold voltage of 1.4 V and thermal impedance of 2.2° C./mW, whereas the 15 μm air-post VCSEL shows a threshold voltage of 7.0V and a thermal impedance of 4.1° C./mw. These differences indicate that in the double intracavity-contacted structure both the injected current and generated heat bypass the AlAsSb/AlGaAsSb DBRs, which have poor thermal and electrical conductivity. These low values eventually decrease the device temperature, resulting in good thermal properties of the VCSELs. The temperature rise in the InP intracavity VCSEL is less than 10° C. at threshold, which is much lower than the air-post VCSELs (>100° C.), even though the aperture, which corresponds to a cross section of current and heat paths, is smaller for the intracavity VCSEL (8 μm) than for the air-post (15 μm).

[0064] Moreover, the voltage and thermal impedance do not change much with the aperture diameter in the double intracavity-contacted structures as can be seen in the air-post structure, and hence the aperture can be made smaller with little increase in the device temperature. Since a vertical flow of the heat or current in the VCSEL depends on the cross section of the aperture, less dependence of the voltage and thermal impedance on the aperture size shows that in the intracavity-contacted VCSELs the InP cladding layers work as current and heat spreaders and a lateral flow in the InP cladding layers is dominant for both the injected current and generated heat.

[0065] Another benefit, low scattering loss, is introduced into the VCSEL 10 by the undercut aperture 30. FIG. 13(a) is a plot of light output characteristics of a double intracavity contacted VCSEL with 16 μm pillar and 8 μm or 12 μm aperture. The VCSEL 10 with the smaller aperture shows not only a lower threshold current, but also a lower threshold current density, a larger differential quantum efficiency and higher output power. In FIG. 13(b), the L-l characteristics are compared between the two VCSELs with the same 10 μm aperture diameter and different pillar diameters. The larger pillar corresponds to the deeper undercut. The temperature rise estimated using the measured thermal impedance and dissipated power is also shown. Since the device temperature is almost the same for both VCSELs, they must experience almost the same free-carrier absorption and the same injection efficiency, both of which strongly depends on the device temperature. Despite this fact, the VCSEL with the larger pillar, i.e. the deeper undercut, shows better performance in the L-l characteristics. By increasing the undercut from 1 μm (12 μm pillar) to 3 μm (16 m pillar), the differential quantum efficiency was increased from 7.2% to 17.5%, and the maximum lasing temperature was increased from 55° C. to 75° C. The deeper undercut reduces more scattering loss at the sidewall of the etched pillar and provides the better L-l characteristics.

[0066] Even with the use of the two InP cladding layers 12 a, 12 b, however, a large amount of heat generated by the active region 14 during performance of the VCSEL dissipates through the second mirror portion 20 instead of through the contacts 22 placed near the active region 14. In one embodiment, a method of heat sinking the VCSEL known as flip-chip bonding is used to provide high heat conductivity through a heat sinking substrate. FIG. 14 is graphical representation showing the reduction in thermal impedance in a VCSEL with flip-chip bonding. In FIG. 14, the substrate 32 is still one of the dominant heat paths, but by heat sinking to the substrate 32, the thermal impedance of the contacts is reduced from measured value of 2.2° C./mW to 1.2° C./mW for a 8 μm aperture. In this embodiment, a metal contact design such as gold-to-gold (Au-to-Au) bonding prevents the increase of thermal impedance due to the bonding of the contacts 22 to the active region 14. Substantial improvement in the thermal impedance results when the VCSEL is flip-chip bonded directly to a heat-sinking substrate with a series of bumps, which may be made of indium phosphide. Heat generated in the active region is conducted to the heat-sink through the InP layers in the bumps, which have a very high thermal conductivity.

[0067] In another embodiment, the VCSEL 10 is etched after all other processing has been completed, including the placement of contacts 22. This is done in order to take advantage of the high selectivity of the citric acid-hydrogen peroxide mixture in the etching of the active region. However, the etch rates of this citric acid-hydrogen peroxide mixture are dramatically affected when contacts are in place, slowing the undercut to 40% of the rate without contacts and therefore slowing the processing rate. Such effects are commonly seen in metal-semiconductor systems since the metal can change the potential of the semiconductor material with respect to the etching solution. FIG. 15 shows one way to overcome these effects by biasing the VCSEL 10 with respect to the solution. In FIG. 15, VCSEL structures with contacts 22 are coupled to a DC power supply 34 and are placed in a citric acid-hydrogen peroxide mixture. When a +5V bias is applied to the VCSEL 10, undercut etching of the InAlGaAs material is decreased. Additionally, the etching of the other n-type material is promoted. The etching rate of the heavily-doped n-type InP is as large as the etching rate of the InAlGaAs. By applying a −5V bias, however, the etching rate of the InAlGaAs not only returns to pre-metal levels but actually is slightly faster.

[0068] Returning to describe the tunnel junction 16 in more detail with reference to FIG. 16, the tunnel junction 16 is partly formed in the InP cladding layer 12 a and partly in the InAlGaAs active region 14. The portion formed in the InP cladding layer 12 a can be designated as the n-type tunnel junction portion 17 and the portion formed in the InAlGaAS active region 14 can be designated as the p-type tunnel junction portion 19. The InP cladding layers 12 a, 12 b are Si n-type doped to a level of 5×10¹⁷ cm³¹ ³. The cladding layers 12 a, 12 b have a heavily-doped contact layers 13, 21 at their upper surfaces. The contact layers 13, 21 can, in one embodiment, be less than 100 Å thick and can be doped with Si to a density of 5×10¹⁸ cm⁻³. The n-type tunnel junction portion 17 can, in one embodiment, be less than 200 Å thick, and in particular can be less than 100 Å thick, and can be doped with Si to a density of 5×10¹⁸ cm⁻³. Thus, the cladding layer 12 a has a doping profile having increased doping levels at each surface. The p-type tunnel junction portion 19 can be less than 200 Å thick, and preferably less than 100 Å thick, and can be composed of InAlAs doped to a level of 1×10²⁰ cm⁻³. The InAlAs can be doped with acceptors such as Carbon, or CBr4, for example.

[0069] The mixture of citric acid and hydrogen peroxide selectively etches away the p-type InAlAs tunnel junction portion 19 along with the InAlGaAs active region 14, but leaves the n-type InP tunnel junction portion 17 substantially in place. This remaining n-type InP tunnel junction portion 17 can be desirable because it provides additional lateral conductivity from the laterally offset contacts 22 to the active region 14.

[0070] The tunnel junction 16 allows for the use of n-doped cladding layers 12 a, 12 b. This results in reduced electrical resistance and reduced free carrier optical absorption than in p-type layers having the same doping level. A VCSEL with n-type cladding layers 12 a, 12 b enabled by the tunnel junction 16 achieves low dissipated power and high differential efficiency simultaneously, resulting in higher power efficiency. The tunnel junction 16 converts the electrons to holes just in time for the active region. In the double intracavity-contacted VCSEL 10 of FIG. 1, where electrical contact is made through the cladding layers 12 a, 12 b, the n-type doping combined with the tunnel junction 16 is particularly beneficial. If one of the cladding layers 12 a, 12 b were a p-type cladding layer then much of the reduction in optical loss from using undoped DBRs would return in the thick p-type cladding layer. Not only is the loss associated with the p-type material greater, but the doping level has to be higher in p-type layers since hole mobility is comparatively low and the layers themselves have to be fairly thick to minimize the electrical resistance. Optical loss in the p-type cladding layers, therefore, is a limiting factor if used in double intracavity-contacted VSCELs. N-type material, on the other hand, has a high electrical conductivity even for low doping levels (and, again, lower loss at those doping levels). The electrical conductivity and optical loss as a function of doping level for the Silicon doped InP, for example, are shown in FIG. 18. The highly doped n-type tunnel diode portion 17 of the cladding layer 12 a is located at a standing-wave null in the laser cavity, minimizing free carrier absorption that would diminish the advantages of the overall low level doping of the cladding layer 12 a. Despite the low doping of the contact layers, the voltage of the VCSEL 10 is very low as shown in FIG. 17. This low doping level also decreases the loss in the structure, enabling high efficiencies also seen in FIG. 17.

[0071] The tunnel junction 16 also serves the important function of spreading current across the aperture, or active region 14. In the present embodiment, the aperture is formed in the active region 14 and the layer 19. However, in other embodiments the aperture can be formed at other locations so long as it confines the current and optical mode. The tunnel junction 16 can also be located at positions other than between the active region 14 and the cladding layer 12 a. For example, the tunnel junction 16 can be formed entirely within the cladding layer 12 a. As shown in FIG. 21, without the tunnel junction the injected current path 29 tends to crowd at the edges 23 of the aperture or active region 14. This is because the current tries to follow the path of least resistance. Thus little of the current passes through the center of the active region 14. This concentrates light generation around the periphery of the device and increases the loss associated with sidewall scattering. It also limits the number of carriers overlapping the fundamental mode of the waveguide. The finite resistance of the quantum well diodes causes some of the carriers to spread but is not large enough to prevent significant crowding. The low, but finite resistance of the tunnel junction 16 of FIGS. 1 and 16 provides a relatively constant potential plane across the entire horizontal cross-section of the aperture or active region 14 to spread the current across the entire aperture. This provides current leveling across the entire aperture.

[0072]FIG. 19 shows I-V plots for three different types of tunnel junctions, including the n-type InP/p-type InAlAs junction described above. The resistivity of these layers is significant compared to the resistivity of one of the cladding layer 12 a. Indium phosphide, one of the materials which is suitable for forming the cladding layer 12 a, has a resistivity of 5.8×10⁻³ ohm-cm for a doping level of only 5×10¹⁷ cm⁻³. Since these tunnel junctions can be made with InAlAs, its derivatives, and InP, they can be etched or oxidized and serve as the aperture layer and also provide a built-in current leveling layer for the aperture.

[0073]FIG. 20 provides an estimate of the current density versus distance dependence which is derived for an InP current spreading layer with an InP/lnAlAs tunnel junction and the aperture in the same layer as the tunnel junction. The calculation is based on a simple resistor network. The plot of FIG. 20 starts at the edge 23 of FIG. 21 at “0 μm” and moves towards the center of the aperture disk formed by the active region 14 at “15 μm”. The disk in this example thus has a diameter of 30 μm. The current remains greater at the edge 23 than at the center of the disk formed by the active region 14, however, the current leveling effect is still significant compared to a device without the tunnel junction and is enough to allow practical intracavity devices. The current density in this example only varies by approximately 60% from the center of the aperture to the edge of the aperture.

[0074] It is to be understood that other embodiments may be utilized and structural and functional changes may be made without departing from the scope of the present invention. The foregoing descriptions of embodiments of the invention have been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Accordingly, many modifications and variations are possible in light of the above teachings. For example, may different sizes of apertures can be used when selectively etching an active region. Also, different amounts of materials used in the design of the various VCSEL components can be used depending on design requirements. Furthermore, the VCSEL may be etched from the substrate up through the bottom mirror portion and bottom cladding layer. It is therefore intended that the scope of the invention be limited not by this detailed description. 

1. A method of enhancing thermal characteristics of a vertical cavity surface emitting laser comprising: providing a double intracavity contacted structure including a first mirror portion, a first cladding layer, a second cladding layer, an active region disposed between the first and second cladding layers, and a second mirror portion; applying a first selective etch to remove at least a portion of the first mirror portion and to expose the first cladding layer; applying a second selective etch to remove at least a portion of the first cladding layer and to expose the active region; and applying a third selective etch to remove at least a portion of the active region to expose the second cladding layer.
 2. The method of claim 1, wherein the first etch removes at least a portion of the first mirror portion and exposes the first cladding layer while leaving a first highly doped contact layer at the surface of the first cladding layer substantially in place.
 3. The method of claim 2, wherein the third etch removes at least a portion of the active region and exposes the second cladding layer while leaving a second highly doped contact layer at the surface of the second cladding layer substantially in place.
 4. The method of claim 1, wherein the first and second cladding layers are heavily doped layers of indium phosphide.
 5. The method of claim 4, wherein the first and second mirror portions include the elements aluminum, arsenic, and antimonide.
 6. The method of claim 5, wherein the first and second mirror portions also include the element gallium.
 7. The method of claim 1, wherein the active region includes the elements indium, phosphorus, aluminum, and gallium.
 8. The method of claim 7, wherein the active region also includes the element arsenic.
 9. The method of claim 1, wherein the first selective etch is a reactive ion etch utilizing chlorine to remove the first mirror portion.
 10. The method of claim 1, wherein the first selective etch stops at the top of the first cladding layer after removing at least of a portion of the first mirror portion.
 11. The method of claim 9, wherein the first selective etch has a selectivity of 6:1.
 12. The method of claim 1, wherein the second selective etch is a reactive ion etch utilizing methane and hyrdogen gases to remove at least a portion of the first cladding layer.
 13. The method of claim 12, wherein the second selective etch also includes argon gas.
 14. The method of claim 1, wherein the second selective etch stops at the top of the active region after removing the first cladding layer.
 15. The method of claim 1, wherein the second selective etch has a selectivity of 16:1.
 16. The method of claim 1, wherein the third selective etch includes a mixture of citric acid and hydrogen peroxide.
 17. The method of claim 16, wherein the third selective etch stops at the top of the second cladding layer after removing at least a portion of the active region.
 18. The method of claim 1, wherein the third selective etch has a selectivity of 80:1.
 19. The method of claim 1, further comprising biasing the double intracavity contacted structure with a +5V DC power supply.
 20. The method of claim 1, further comprising biasing the double intracavity contacted structure with a −5V DC power supply.
 21. The method of claim 1, wherein applying the third selective etch includes placement of the double intracavity contacted structure in a mixture of citric acid and hydrogen peroxide.
 22. The method of claim 21, wherein a +5V power supply is applied to the double intracavity contacted structure while the structure is placed in said mixture.
 23. The method of claim 21, wherein a −5V power supply is applied to the double intracavity contacted structure while the structure is placed in said mixture.
 24. The method of claim 1, wherein at least a portion of the active region is removed to form an undercut aperture between the first and second mirror portions.
 25. A method of manufacturing a vertical cavity surface emitting laser, the method comprising: providing a double intracavity contacted semiconductor device including a first mirror portion, a first indium phosphide (InP) cladding layer, a second InP cladding layer, an active region disposed between the first and second cladding layers, and a second mirror portion; removing the first mirror portion from the device using a first selective reactive ion etch; and removing the first InP cladding layer from the device using a second selective reactive ion etch.
 26. The method of claim 25, wherein the first etch removes at least a portion of the first mirror portion and exposes the first cladding layer while leaving a first highly doped contact layer at the surface of the first cladding layer substantially in place.
 27. The method of claim 25, wherein at least a portion of the active region is removed to form an undercut aperture between the first and second mirror portions.
 28. The method of claim 27, wherein the undercut aperture is formed using a citric peroxide selective etch.
 29. The method of claim 27, wherein the undercut aperture is formed by introducing an insulating oxide layer into the active region.
 30. The method of claim 25, wherein removing the first mirror portion includes etching at least a portion of the first mirror portion with the first selective etch.
 31. The method of claim 25, wherein removing the first InP cladding layer includes etching at least a portion of the first InP cladding layer with the second selective etch.
 32. The method of claim 25, wherein the first and second mirror portions are multi-layer materials including the elements aluminum, arsenic, and antimonide.
 33. The method of claim 32, wherein the first and second mirror portions also include the element gallium.
 34. The method of claim 25, wherein the active region includes the elements indium, phosphorus, aluminum, and gallium.
 35. The method of claim 25, wherein the active region also includes the element arsenic.
 36. The method of claim 25, wherein the first selective etch includes chlorine.
 37. The method of claim 25, wherein the first selective etch stops at the top of the first cladding layer after removing the first mirror portion from the device.
 38. The method of claim 25, wherein the first selective etch has a selectivity of 6:1.
 39. The method of claim 25, wherein the second selective etch includes methane and hyrdogen.
 40. The method of claim 39, wherein the second selective etch further includes argon.
 41. The method of claim 25, wherein the second selective etch stops at the top of the active region after removing the first cladding layer from the device.
 42. The method of claim 25, wherein the second selective etch has a selectivity of 16:1.
 43. The method of claim 28, wherein the citric peroxide selective etch stops at the top of the second InP cladding layer after removing at least a portion of the active region from the device.
 44. The method of claim 28, wherein the citric peroxide selective etch has a selectivity of 80:1.
 45. The method of claim 27, further comprising biasing the double intracavity contacted structure with a +5V DC power supply as the active region is being removed.
 41. The method of claim 27, further comprising biasing the double intracavity contacted structure with a −5V DC power supply as the active region is being removed. 